FPGA’s Accelerating Image Processing 2017

Although computers keep getting faster and faster, there are always new image processing algorithms than is available. Examples of current high-demand applications include real-time video stream encoding and decoding, real-time biometric (face, retina or fingerprint) recognition, and military aerial and satellite surveillance applications. To meet the demands of these future applications, we need to develop new techniques for accelerating image-based applications on commercial hardware.

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Currently, image processing applications are implemented on general purpose processors such as Pentiums. In some cases, applications are implemented on digital signal processor (DSPs), and in extreme cases (when economics permit) applications can be implemented in Application Specific Integrated Circuits (ASICs). Now compiler technology can be used to map image processing algorithms onto FPGAs, achieving 8 to 800 fold speed-ups over Pentiums.

Field-programmable gate arrays are non-conventional processors built almost entirely out of lookup tables. In particular, FPGAs contain grids of logic blocks connected by programmable wires. Each logic block has one or more Look-Up Tables (LUTs) and several bits of memory. As a result, logic blocks can implement arbitrary logic functions or be combined together to form registers. FPGAs as a whole can be used to implement circuit diagrams, by mapping the gates and registers onto logic blocks. FPGAs were originally developed to serve as test vehicles for hardware circuit designs. Recently, however, FPGAs have become so dense and fast that they have evolved from a simple test and “glue logic” circuits into the central processors of powerful reconfigurable computing systems.

The economics of FPGAs are fundamentally different from the economics of other parallel architectures. Because of the comparatively small size of the image processing market, most special purpose image processors have been unable to keep pace with advances in general purpose processors. FPGAs, on the other hand, enjoy a multi-billion dollar market as low-cost ASIC replacements.

Unfortunately, FPGAs are very difficult to program. Algorithms must be expresses as detailed circuit diagrams, including clock signals etc. This discourages most computer vision researchers from exploiting FPGAs, the intrepid few who do are repeatedly frustrated by the laborious process of modifying or combining FPGA circuits.

The SA-C language and compiler allow FPGAs to be programmed in the same way as other processors. Programs are written in a high-level language and can be compiled, debugged, and executed from a local workstation. It so happens that for SA-C programs the host executable off loads the processing loops onto an FPGA, but this is invisible. SA-C, therefore, makes reconfigurable processors accessible to applications programmers with no hardware expertise.

The question is whether image processing tasks run faster on FPGAs than on conventional general purpose hardware, in particular Pentiums. Simple image operators are faster on reconfigurable processors because of their greater capabilities for I/O between the FPGA and local memory, although this speed up is modest. More complex tasks result in larger speed ups, up to a factor of 800, by exploiting the parallelism within FPGAs and the strengths of an optimizing compiler.

For many years, real-time applications on traditional processors had to be written assembly code, because the code generated by compilers was not as efficient. In particular, the FPGA configurations generates by the SA-C compiler currently use only one clock signal. This limits the I/O ports to operate at the same speed as the computational circuit. Xilinx FPGAs, however, support multiple clocks running at different speeds and include internal RAM blocks that serve as data buffers.

FPGAs are a class of processors with two billion dollar market per year. As a result they obey Moore’s Law, getting faster and denser at the same rate as other processors. This states that most image processing applications run faster on FPGAs than on general purpose processor and that this will continue to be true as both types of processors become faster.

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Ritesh
administrator
Ritesh Kanjee has over 7 years in Printed Circuit Board (PCB) design as well in image processing and embedded control. He completed his Masters Degree in Electronic engineering and published a paper for IEEE called Vision-based adaptive Cruise control using Pattern matching (on Google Scholar). His work was implemented in LabVIEW. He works as an Embedded Electronic Engineer in defence research. He has experience in FPGA design with programming in both VHDL and Verilog.