Xilinx Vivado: Beginners Course to FPGA Development in VHDL

  • Admin bar avatar
  • 1367 (Register)
  • (0 Review)



Do you want to learn the new Xilinx Development Environment called Vivado Design Suite?  Are you migrating from the old ISE environment to Vivado? Or are you new to FPGA’s? This course will teach you all the fundamentals of the Vivado Design Suite in the shortest time so that you can get started developing on FPGA’s.

Now why should you take this course when Xilinx Official Partners already offer training? Most of their course are held bi-annually which means you will have to wait at most 6 months before starting the basic training. Also these courses can cost over thousands of dollars.

My Name is Ritesh Kanjee and I am an FPGA Designer with a Masters Degree in Electronic Engineering. I have over 7300 students on Udemy. This course is designed to help you design, simulate and implement HDL code in Vivado through practical and easy to understand labs. You will learn all the fundamentals through practice as you follow along with the training. Together we will build a strong foundation in FPGA Development with this training for beginners.

This course will enable you to:

  • Build an effective FPGA design.
  • Use proper HDL coding techniques
  • Make good pin assignments
  • Set basic XDC constraints
  • Use the Vivado to build, synthesize, implement, and download a design to your FPGA.

Training Duration

1 hour


After Completing this Training, you will know how to:

  • Design for 7 series+ FPGAs
  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based)
  • Identify file sets such as HDL, XDC and simulation
  • Analyze designs by using Schematic viewer, and Hierarchical viewer
  • Synthesize and implement a simple HDL design
  • Build custom IP cores with the IP Integrator utility
  • Build a Block RAM (BRAM) memory module and simulate the IP core
  • Create a microblaze processor from scratch with a UART module
  • Use the primary Tcl Commands to Generate a Microblaze Processor
  • Describe how an FPGA is configured.

Course Curriculum

Total learning: 15 lessons Time: 1 hour
  • Introduction to Vivado  3 lessons 0/3

  • Lab 1  4 lessons 0/4

    • Introduction to the Vivado Design Suite Interface and Creating a New Project 7 minute
    • Coding and Simulating Simple VHDL in Vivado 8 minute
    • Implementation of VHDL Design in Vivado and IO Pin Planning 9 minute
    • Downloading the Bit-stream to the FPGA 2 minute
  • Lab 2  2 lessons 0/2

  • Lab 3  3 lessons 0/3

    • Designing a Microblaze Soft Processor in Vivado IP Integrato 10 minute
    • Generating a Microblaze using TCL commands in Vivado 4 minute
    • Learn VHDL by Example 4 minute
  • Conclusion and Bonus Section  3 lessons 0/3

Ritesh Kanjee has over 7 years in Printed Circuit Board (PCB) design as well in image processing and embedded control. He completed his Masters Degree in Electronic engineering and published a paper for IEEE called Vision-based adaptive Cruise control using Pattern matching (on Google Scholar). His work was implemented in LabVIEW. He works as an Embedded Electronic Engineer in defence research. He has experience in FPGA design with programming in both VHDL and Verilog.



0 rating

5 stars
4 stars
3 stars
2 stars
1 star