Xilinx Vivado: Beginners Course to FPGA Development in VHDL
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Do you want to learn the new Xilinx Development Environment called Vivado Design Suite? Are you migrating from the old ISE environment to Vivado? Or are you new to FPGA’s? This course will teach you all the fundamentals of the Vivado Design Suite in the shortest time so that you can get started developing on FPGA’s.
Now why should you take this course when Xilinx Official Partners already offer training? Most of their course are held bi-annually which means you will have to wait at most 6 months before starting the basic training. Also these courses can cost over thousands of dollars.
My Name is Ritesh Kanjee and I am an FPGA Designer with a Masters Degree in Electronic Engineering. I have over 7300 students on Udemy. This course is designed to help you design, simulate and implement HDL code in Vivado through practical and easy to understand labs. You will learn all the fundamentals through practice as you follow along with the training. Together we will build a strong foundation in FPGA Development with this training for beginners.
This course will enable you to:
- Build an effective FPGA design.
- Use proper HDL coding techniques
- Make good pin assignments
- Set basic XDC constraints
- Use the Vivado to build, synthesize, implement, and download a design to your FPGA.
After Completing this Training, you will know how to:
- Design for 7 series+ FPGAs
- Use the Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based)
- Identify file sets such as HDL, XDC and simulation
- Analyze designs by using Schematic viewer, and Hierarchical viewer
- Synthesize and implement a simple HDL design
- Build custom IP cores with the IP Integrator utility
- Build a Block RAM (BRAM) memory module and simulate the IP core
- Create a microblaze processor from scratch with a UART module
- Use the primary Tcl Commands to Generate a Microblaze Processor
- Describe how an FPGA is configured.
Course Curriculum%Total learning: 15 lessons Time: 1 hour
Introduction to Vivado 3 lessons
- Introduction 2 minute
- 1 minute
- How to Download and Install Xilinx Vivado Design Suite 6 minute
Lab 1 4 lessons
- 7 minute
- 8 minute
- 9 minute
- 2 minute
Lab 2 2 lessons
- Design a Block RAM in IP Integrator 7 minute
- 5 minute
Lab 3 3 lessons
- 10 minute
- 4 minute
- Learn VHDL by Example 4 minute
Conclusion and Bonus Section 3 lessons
- 5 minute
- Questions from Students (Bonus Lecture) 4 minute
- 1 minute